The present invention relates to a semiconductor memory device and a method for fabricating the same, and more particularly, to a non-volatile memory device and a method for fabricating the same.
A non-volatile memory device is capable of retaining stored data even when power to the memory device is turned off. In particular, since the non-volatile memory device stores data by supplying charges into a floating gate electrode, it is referred to as a floating gate non-volatile memory device.
Herein, the non-volatile memory device includes a cell region and a peripheral circuit region. While a gate pattern of the cell region stores data by supplying or releasing charges into or from the floating gate electrode, a gate pattern of the peripheral circuit region operates as a typical transistor. Therefore, when forming the gate patterns, there is required a process of forming a contact hole in a charge blocking layer of the peripheral circuit region to connect the floating gate electrode and a control gate electrode.
Hereinafter, a method for fabricating a non-volatile memory device according to the prior art and its problems will be described with reference to figures.
FIG. 1 illustrates a layout of the non-volatile memory device according to the prior art.
Referring to FIG. 1, an active region A is defined by a device isolation layer formed as a line type that is disposed in a field region F. On a substrate, a bit line BL is disposed in a first direction A-A′ and a plurality of source selection lines SSL and a plurality of drain selection lines DSL are disposed in a second direction B-B′ intersecting with the first direction A-A′. Furthermore, a plurality of word lines WL is disposed between the source selection lines SSL and the drain selection lines DSL.
Herein, the source selection lines SSL connect gate electrodes of source selection transistors and a common source line CSL is disposed in a junction region between the source selection lines SSL. The drain selection lines DSL connect gate electrodes of drain selection transistors and drain contact plugs DCT are disposed in a junction region between the drain selection lines DSL.
The source selection lines SSL or the drain selection lines DSL are formed in the peripheral circuit region to operate as typical transistors, and memory cells storing data are formed in the cell region.
FIGS. 2A to 2E illustrate sectional views explaining a method for fabricating the non-volatile memory device according to the prior art and cross-sectional views taken along the first direction A-A′ of FIG. 1.
Referring to FIG. 2A, after forming a tunnel insulation layer 21 and a conducting layer for a floating gate electrode on a substrate 20, a plurality of floating gate electrode patterns 22 extending parallel to the first direction A-A′ is formed performing a patterning process and a process of forming a device isolation layer.
Then, a charge blocking layer 23 and a protection layer 24 are formed on the floating gate electrode pattern 22. Herein, the protection layer 24 is formed to prevent the charge blocking layer 23 from being damaged in a subsequent process of forming a contact hole in the charge blocking layer 23.
Subsequently, a charge blocking layer contact mask 25 is formed on the protection layer 24. At this point, the charge blocking layer contact mask 25 is formed to expose a peripheral circuit region, e.g., a portion of a region where selection lines are to be formed. This is to connect floating gate electrodes and control gate electrodes that are to be formed in the peripheral circuit region in subsequent processes and thus make the selection lines of the peripheral circuit region operate as normal transistors.
Referring to FIG. 2B, a charge blocking layer contact hole is formed by etching the protection layer 24 and the charge blocking layer 23 using the charge blocking layer contact mask 25 as an etch barrier. In this figure, a protection layer including the charge blocking layer contact hole is indicated by a reference numeral 24A and a charge block layer including the charge blocking layer contact hole is indicated by a reference numeral 23A.
After forming a conducting layer 26 and a hard mask layer 27 on a resultant structure including the charge blocking layer contact hole, a mask pattern 28 is formed on the hard mask layer 27.
Referring to FIG. 2C, the hard mask layer 27, the conducting layer 26, the protection layer 24A, the charge blocking layer 23A and the floating gate electrode pattern 22A are sequentially etched using the mask pattern 28 as an etch barrier.
As a result, a gate pattern including the tunnel insulation layer 21, an etched floating gate electrode pattern 22A, an etched charge blocking layer 23B, an etched protection layer 24B and an etched conducting layer 26A is formed, wherein the etched floating gate electrode pattern 22A is referred to as a floating gate electrode and the etched conducting layer 26A is referred to as a control gate electrode hereinafter. Herein, in the gate pattern formed in the peripheral circuit region, the floating gate electrode 22A and the control gate electrode 26A are connected to each other by the contact hole.
Referring to FIG. 2D, after an oxide spacer 29 is formed on a sidewall of the gate pattern, a nitride spacer 30 is formed on the whole surface of a resultant structure including the oxide spacer 29.
After forming a first inter-layer insulation layer 31 on the whole surface of a resultant structure including the nitride spacer 30, a planarization process is performed on the first inter-layer insulation layer 31 until a top surface of the nitride spacer 30 is exposed.
Referring to FIG. 2E, the first inter-layer insulation layer 31, the nitride spacer 30 and the oxide spacer 29 are etched back to a given depth from a top surface of the gate pattern to expose a portion of the control gate electrode 26A.
Then, a metal silicide control gate electrode 26B is formed by performing a metal silicidation process on the partially exposed control gate electrode 26A.
Subsequently, a second inter-layer insulation layer 32, a nitride spacer 33 and a third inter-layer insulation layer 34 are sequentially formed on the whole surface of a resultant structure including the metal silicide control gate electrode 26B.
The third inter-layer insulation layer 34, the nitride spacer 33, the second inter-layer insulation layer 32, the first inter-layer insulation layer 31, the nitride spacer 30 and the tunnel insulation layer 21 are selectively etched to form a contact hole that exposes a portion of the substrate 20 disposed between the gate patterns formed in the peripheral circuit region. Then, a contact plug is formed by filling the contact hole with a conducting layer 35.
According to the prior art as described above, the floating gate electrode 22A and the control gate electrode 26B of the gate pattern formed in the peripheral circuit region are connected to each other through the process of forming the charge blocking layer contact hole. That is, while a memory cell is formed by separating the floating gate electrode 22A from the control gate electrode 26B in a cell region, a selection line may be formed by connecting the floating gate electrode 22A and the control gate electrode 26B in the peripheral circuit region.
However, according to the prior art, since there is required the process of forming the charge blocking layer contact hole, the fabricating process is complicated and thus there is limitations in improving a degree of integration of a memory device. Problems of the prior art will be described in detail hereinafter.
First of all, since an area is reduced by the improvement of the degree of integration of the memory device, it is difficult to allocate the charge blocking layer contact mask 25 in a desired position and perform an etching process. That is, it is not easy to form the contact hole and thus the probability, that the transistors formed in the peripheral circuit region abnormally operate, increases.
Second, there occurs the signal delay. Since the contact hole is formed by etching a portion of the charge blocking layer 23 when forming the gate pattern in the peripheral circuit region, the floating gate electrode 22A cannot be connected to the control gate electrode 26B as one body through all of them and they are connected to each other through a contact formed in their portions. Therefore, the signal delay occurs by the contact resistance and the performance of the memory device is deteriorated since the signal delay further increases in a region far from the contact.
Third, an electrical characteristic of the memory device changes since an interface between the protection layer 24B and the control gate electrode 26B becomes unstable. Herein, the protection layer 24B is formed on the charge blocking layer 23B to prevent the damage of the charge blocking layer 23B when forming the contact hole, and the protection layer 24B is typically formed of polysilicon. Like this, since the control gate electrode 26B is formed on the resultant structure including the contact hole that is formed by etching the protection layer 24B and the charge blocking layer 23B, the interface between the protection layer 24B and the control gate electrode 26B becomes unstable and thus the performance of the memory device is deteriorated.
Meanwhile, according the prior art, the gate pattern including the tunnel insulation layer 21, the floating gate electrode 22A, the charge blocking layer 23B, the protection layer 24B and the control gate electrode 26B is formed in any of the cell region and the peripheral circuit region.
Therefore, since the height of the gate pattern is great, there may be generated an empty region, i.e., a void, that is not filled up in the process of filling a gap region between gate patterns with the first inter-layer insulation layer 31. For instance, a void may be generated in the gap region between the gate patterns when filling the gap region with the first inter-layer insulation layer 31, referring to a reference numeral {circle around (1)} in FIG. 2D, or a void may be generated in the process of filling the contact hole with the conducting layer 35 to form the contact plug, referring to a reference numeral {circle around (2)} in FIG. 2E.
The above phenomenon is usually caused in a gap region between gate patterns in a decoder region or a gap region between drain selection lines. This induces a defective like a short circuit between adjacent drain contacts in a subsequent process of forming the drain contacts.
FIG. 2F illustrates a plane view of a region where a drain contact is formed according to the prior art.
Referring to a process of forming the drain contact, after forming a contact hole exposing a portion of a substrate between drain selection lines by etching layers such as an inter-layer insulation layer, a drain contact plug is formed by filling the contact hole with a conducting layer.
At this point, referring to the reference numeral {circle around (2)} in FIG. 2E and a reference numeral {circle around (3)} in FIG. 2F, adjacent drains may be connected to each other by a void generated in the process of filling the contact hole with the conducting layer and thus the defective like the short circuit may be caused.